(1) Field of the Invention
The present invention generally relates to a device and method for estimating a sampled value of an impulse response. Such a device and method are used for a signal reproduction procedure in a digital transmission system. Further, the present invention is concerned with a signal reproduction system using such a device.
(2) Description of the Related Art
Generally, the waveform of a signal distorts and attenuates during digital transmission. Thus, so-called three R functions (Retiming, Reshaping and Regeneration) are needed in the techniques of digital transmission.
FIG. 1 is a block diagram of a conventional signal reproduction circuit used in a digital transmission system. The signal reproduction circuit is composed of a waveform equalizing circuit 101, a timing reproduction circuit 102, and a decision circuit 103. The waveform equalizing circuit 101 equalizes the waveform of a digital signal transmitted via an incoming line (reshaping function). The timing extraction or reproduction circuit 102 reproduces a timing clock (retiming function) from an equalized (reshaped) digital signal output by the waveform equalizing circuit 101. The decision circuit 103 performs a decision procedure on the equalized digital signal by using the reproduced timing clock output by the timing reproduction circuit 102, and outputs a reproduced digital signal to an outgoing line (regeneration function).
The timing reproduction circuit 102 generates the timing reproduction clock as shown in FIG. 2(a) on the basis of an eye in, for example, an equalized AMI (Alternate Mark Inversion) output. The decision circuit 103 detects the mark or space of the equalized AMI output at each rise (decision point) of the reproduced timing clock, and generates a reproduced output (NRZ (Non Return to Zero) output), as shown in FIG. 2(b).
Conventionally, the timing reproduction circuit 102 is comprised of an analog circuit, as shown in FIG. 3. The analog circuit shown in FIG. 3 extracts a signal portion of the AMI waveform around only each peak value thereof by a full-wave rectification circuit 102-1. Then, a full-wave rectified output from the circuit 102-1 as shown in FIG. 4(a) is input, via a resistor R, to an LC tank circuit 102-2, which is made up of an inductor L and a capacitor C. The LC tank circuit 102-2 generates a sine wave corresponding to a desired clock frequency, as shown in FIG. 4(b). The sine wave output by the LC tank circuit 102-2 is shaped by a limiter amplifier 102-3, which generates the aforementioned reproduced timing clock, as shown in FIG. 4(c).
However, there is a disadvantage in that it is necessary to use a large-size coil in order to form the LC tank circuit 102-2. In addition, the configuration shown in FIG. 3 cannot extract the timing signal from the AMI signal or a series of spaces (zeros).
In order to eliminate the above-mentioned disadvantages, a timing reproduction circuit using a digital phase-locked loop (DPLL) has been proposed. A conventional DPLL is shown in FIG. 5. The DPLL shown in FIG. 5 is made up of a phase comparator 201, a frequency divider 202, and a master clock generator 203. The master clock generator 203 generates a master clock having a frequency (20.48 MHz, for example) more than 100 times a necessary clock frequency (80 kHz, for example). The frequency divider 202 divides the frequency of the master clock in order to generate a clock having the necessary clock frequency. The phase of the clock generated by the frequency divider 202 is compared with the phase of an input signal. The frequency dividing ratio in the frequency divider 202 is adjusted based on the phase difference between the signals input to the phase comparator 201.
FIG. 6 shows a signal reproduction circuit which uses a DPLL as described above. The signal reproduction circuit shown in FIG. 6 is composed of a waveform equalizing circuit 1, a timing reproduction circuit 2 and a decision circuit 3. The waveform equalizing circuit 1 is made up of an automatic gain controller (AGC) 11 and a decision feedback type equalizer 12. The AGC 11 receives an input signal in digital form and automatically adjusts the gain of the input signal to a fixed level. The equalizer 12 corrects the output of the AGC 11 on the basis of input and output signals of the decision circuit 3, as will be described in detail later.
The timing reproduction circuit 2 generates a reproduced timing clock from an equalized signal output by the waveform equalizing circuit 1, and is composed of a sampled value estimating formula evaluation unit 21, a controller 22, a frequency divider 23 and a master clock generator 24. The evaluation unit 21 estimates an impulse response waveform of each isolated pulse contained in the input signal, and extracts information about the phase of the estimated impulse response waveform. The nth sampled value of the impulse response, labeled hn, is estimated as follows: ##EQU1## where fn is the nth value in a train of sampled values of the input signal (equalized outputs), and a.sub.n-k is a train of decided values of the input signal. Formula (1) can be modified as follows: ##EQU2##
It will be noted that the items after the second item a.sub.n-1 .multidot.a.sub.n-1 .multidot.h.sub.1 are values smaller than the second item and positive or negative signs at random. Thus, the summation of the items after the second item converges to zero. As a result, the average value of a.sub.n-1 .multidot.fn, E[a.sub.n-1 .multidot.fn] is as follows: EQU E[a.sub.n-1 .multidot.f.sub.n ]=E[a.sub.n-1.sup.2 .multidot.h.sub.q ]=h.sub.1 .multidot.E[a.sub.n-1.sup.2 ] (3).
Thus, h.sub.1 can be written as follows: EQU h1=E[an-1.multidot.fn]/E[an-1.sup.2 ] (4)
In the above-mentioned way, it is possible to estimate the first sampled value h.sub.1 of the train of sampled values of the impulse response at the sampling point.
FIG. 7(a) shows an input pulse, and FIG. 7(b) shows an impulse response thereto. The first sampled value h.sub.1 of the impulse response is estimated by the above-mentioned formula (4).
As shown in FIG. 8(a), a threshold value hth is determined. When the sampling point is at a correct position, the first sampled value h.sub.1 is equal to the threshold value hth. At this time, the sampling point is positioned at a left shoulder portion of a main response contained in the impulse response. The difference between the first sampled value h.sub.1 and the threshold value hth is calculated. When the sampled value h.sub.1 is larger than the threshold value hth, as shown in FIG. 8(b), the sampling point is too delayed. On the other hand, when the sampled value h.sub.1 is smaller than the threshold value hth, as shown in FIG. 8(c), the sampling point is too advanced.
FIG. 9 is a block diagram of the sampled value estimating formula evaluation unit 21. As shown in FIG. 9, the evaluation unit 21 is composed of multipliers 21-1 and 21-2, switches 21-3 - 21-5, an adder 21-6, a delay element (T) 21-7, registers 21-8 and 21-9, a output sample f.sub.n and the decided value sample an-1. The multiplier 21-2 calculates the square a.sub.n-1.sup.2 of the decided value sample an-1. The switch 21-3 has two switches 21-3a and 21-3b, which operate in opposite switching modes. The switch 21-3a controls the passage of the output f.sub.n .multidot.a.sub.n-1 from the multiplier 21-1, and the switch 21-3b controls the passage of the output a.sub.n-1.sup.2 from the multiplier 21-2. The switches 21-4 an 21-5 are used for controlling the inputting of the values calculated by the adder 21-6 to the registers 21-8 and 21-9, respectively, and operates in the opposite switching modes. The switch 21-4 has two switches 21-4a and 21-4b, and the switch 21-5 has two switches 21-5a and 21-5b. The switch 21-3a and the switch 21-4 operate in the same switching mode, and the switch 21-3b and the switch 21-5 operate in the same switching mode.
The adder 21-6 adds the (n-1) th calculated value and the (n-2)th calculated value. The delay element 21-7 delays the output of the adder 21-6 by a predetermined time. The register 21-8 is used for storing E[a.sub.n-1 .multidot.f.sub.n ], and the register 21-8 is used for storing E[a.sub.n-1.sup.2 ]. The comparator 21-10 compares E[a.sub.n-1 .multidot.f.sub.n ] read out from the register 21-8 with E[a.sub.n-1.sup.2 ] read out from the register 21-9. It can be seen from the above that the circuit shown in FIG. 9 uses the threshold value hth equal to 1. The controller 21-11 controls the comparison timing of the comparator 21-11, clears the registers 21-8 and 21-9, and controls the switches 21-3 - 21-5.
During operation, the product fn.an-1 is calculated by the multiplier 21-1, and the square a.sub.n-1.sup.2 of the decided value an-1 is calculated by the multiplier 21-2. The switches 21-3a, 21-4a and 21-4b are closed first. Thereby, an updating value for calculating the average of fn.multidot.an-1 is stored in the register 21-8. Next, the switches 21-3b, 21-5a and 21-5b are closed. Thereby, an updating value for calculating the average of a.sub.n-1.sup.2 is stored in the register 21-9. After that, E[a.sub.n-1 .multidot.f.sub.n ] and E[a.sub.n-1.sup.2 ] respectively read out from the registers 21-8 and 21-9 are compared with each other by the comparator 21-10 in response to a control signal output by the controller 21-11. Then, the comparator 21-10 outputs information indicating which E[a.sub.n-1 .multidot.f.sub.n ] or E[a.sub.n-1.sup.2 ] is greater (or smaller) than the other. When the comparator 21-10 executes the above-mentioned comparing operation, the contents of the registers 21-8 and 21-9 are cleared.
Returning now to FIG. 6, the evaluation unit 21 generates a control signal for adjusting the frequency dividing ratio in the frequency divider 23 on the basis of the comparison results output by the evaluation unit 21. The frequency divider 23 divides the frequency of a master clock generated by the master clock generator 24. The frequency dividing ratio is controlled by the control signal output by the controller 22. The clock signal output by the frequency divider 23 is input, as the reproduced timing clock, to the decision circuit 3, and is also input to the AGC 11, the equalizing circuit 12 and the evaluation unit 21.
The decision circuit 3 shown in FIG. 6 carries out the decision procedure on the equalized signal output by the waveform equalizing circuit 1 by using the timing reproduction signal output by the timing reproduction circuit 2, so that the reproduced digital signal can be generated. The timing reproduction circuit 2 estimates the impulse response waveform from the equalized output, and compares the estimated sampled value h1 with the threshold value hth in order to adjust the frequency dividing ratio. The frequency divider 23 outputs the reproduced timing clock to the decision circuit 3 in accordance with the adjusted frequency dividing ratio. The decision circuit 3 detects the mark or space of each equalized impulse response at a decision point (sampling point) which is at each rise of the reproduced timing clock, so that the reproduced output is generated by the decision circuit 3.
However, a conventional system as described above has a disadvantage in that it is necessary to calculate the products a.sub.n-1.sup.2 and an-1.sup.2 in order to estimate the sampled value of each impulse response. Nowdays, the reproduction/repeater function can be implemented one one-chip VLSI. However, the multiplier needs an extremely large scale integrated circuit having, for example, thousands of gates, each having a 16 bit .times.16 bit scale.